Government Adopts Multi-Pronged Roadmap to Build a Robust Semiconductor Talent Pipeline Across Design, Manufacturing and Advanced Packaging

The Ministry of Electronics & IT announced a multi‑pronged roadmap under the Semicon India Programme (Semicon 2.0) to create a semiconductor talent pipeline covering design, manufacturing and advanced packaging. Initiatives include the Chips to Startup (C2S) programme offering free access to EDA tools (over 240 lakh tool‑hours used), the SMART Lab at NIELIT Calicut training more than 1 lakh engineers in VLSI, Embedded Systems and IoT, and the establishment of an ATMP training laboratory at NIELIT Guwahati. Over 68,000 individuals have been skilled in chip design and 175 designs have been taped out. Semicon 2.0, approved on 15 July 2026, carries an outlay of ₹1.275 lakh crore and includes industry and international partnerships for further skill development.